System with a clocked interface

ABSTRACT

A system with a transmitter for transmitting digital data via an interface to a receiver. The interface has at least one data line and a clock line. A clock generator supplies a clock signal to the clock line. The receiver uses the clock signal received from the clock line for deriving timing information for processing received digital data. The clock signal may have an amplitude that is lower than the power supply voltage VDD, typically less than half of the power supply voltage, and less stringent requirements can be applied to the waveform of the clock signal than traditionally applied to data and clock signals. The clock signals are hereby less power consuming and cause significantly less electromagnetic interference.

The invention relates to digital systems with one or more unitscommunicating digital data via an interface, where the interface has oneor more data lines for transmitting digital data and a clock linetransmitting clock signals with timing information for use by a receiverreceiving the digital data from the interface.

Conventional synchronous high-speed serial bus systems require a clocksignal, whenever an exchange of digital data between a data transmitterand a data receiver is done over the interface. The clock signals usedin such systems are square wave signals with an amplitude substantiallyequal to the power supply voltage VDD of the system.

Such square wave clock signals are power consuming, and they contain asubstantial amount of harmonic frequencies due to the square waveform ofthe clock signal. The harmonic frequencies may cause disturbances due toelectromagnetic interference (EMI), and measures have to be taken inorder to protect sensitive equipment and components against EMI.

U.S. Pat. No. 4,021,740 discloses a sine wave clock distributionnetwork, i.e. a sine wave system clock. The sine wave system clock isconnected through a branching network to a plurality of clock driverslocated in the vicinity of digital circuits to which clock pulses are tobe supplied.

A typical known system is illustrated in FIG. 1, where a masterintegrated circuit (IC) transmits digital data over a serial interface,and a slave IC receives the data transmitted by the master IC. A systemclock signal is supplied both to the master IC and to the slave IC, andin both integrated circuits the received clock signal is processed orregenerated to have suitable properties for use in the respectiveintegrated circuit. The system clock signal can thus be any appropriatesignal such as a square wave or a sine wave, and each of the integratedcircuits performs its own processing of the system clock signal. In themaster IC the serial interface receives the processed clock signal andtransmits the processed clock signal on a clock line with timinginformation for use by the slave IC. The slave IC receives the clocksignal together with the digital data from the master IC. It is seenthat the slave IC receives two clock signals, the system clock signaland the clock signal from the master IC. This requires at least one pinon the integrated circuit for each clock signal. Furthermore, andtraditionally, the clock signal transmitted from the master IC to theslave IC is a square wave signal with an amplitude substantially equalto the power supply voltage VDD of the system, which may causedisturbances due to electromagnetic interference (EMI).

It is the object of the invention to provide a system, which is lesssusceptible of causing disturbances due to EMI. It is also an object ofthe invention to provide a system with less power dissipation. Anotherobject of the invention is to provide a system, which requires lessinput terminals or pins on the integrated circuits of the system.

These objects are achieved by a system according to the invention, inwhich the receiver uses the clock signal received from the clock linefor deriving timing information for processing received digital data.

FIG. 1 shows a prior art system,

FIG. 2 shows schematically one preferred embodiment of the invention,

FIG. 3 shows schematically another preferred embodiment of theinvention,

FIG. 4 shows schematically a possible implementation of the invention,and

FIG. 5 shows schematically an example of the signal waveforms in thesystem shown in FIG. 4.

FIG. 2 shows a system with a master integrated circuit (IC) and a slaveintegrated circuit (IC). A communication bus with at least one serialdata line and a clock line interconnects the master IC and the slave IC.The slave IC and the master IC exchange digital data over the data line.The exchange of data can be unidirectional from the master IC as datatransmitter to the slave IC as data receiver only, or it can bebi-directional with either IC as transmitter and the other IC asreceiver. A system clock generator generates a system clock signal,which is supplied to the clock line of the interface bus, and both themaster IC and the slave IC receive the system clock signal. The masterIC and the slave IC both receive a power supply voltage VDD. As shown,the power supply voltage VDD can be supplied from a common source, or itcan be supplied from different sources. As in the prior art system ofFIG. 1, the system clock supplied to the clock line of the interface buscan be a sine wave signal or any stable periodic signal with afundamental frequency of the desired clock frequency. Here, the systemclock signal alternates between two voltage levels with a differencesmaller than the power supply voltage VDD, preferably less than halfthereof.

Such clock signals are here referred to as “low swing” signals, whichinclude all signals, which change state at levels, which are lower thanthe supply voltage VDD of the circuit they are connected to. In order touse this low swing signal, the integrated circuits need to regeneratethe signal by amplification and re-shaping. A typical low swing signalcan be a sinusoidal wave, which has an amplitude of VDD/2.

As opposed to “low swing” signals, “full swing” refers to a signal,which toggles (=changes state) at the same level as supply voltage ofthe circuit it is attached to. A typical full swing signal is a squarewave with amplitude VDD—the edges of such a signal are steep and aresusceptible of producing noise in the system through EMI.

FIG. 3 shows another embodiment of the invention. In contrast to theembodiment in FIG. 2, the system in FIG. 3 does not utilize a systemclock generator but a clock generator internal to the master IC. Theinternal clock generator generates a clock signal, which can be a “lowswing” clock signal. The clock signal from the internal clock generatoris supplied to a clock processing circuit to be regenerated for furtheruse in the master IC, and to a serial interface in the master IC. Theslave IC is in all relevant aspects identical to the slave IC in FIG. 2,and the exchange of data can be unidirectional from the master IC to theslave IC only or bi-directional. In this embodiment the clock signal istransmitted as a “low swing” clock signal from the master IC, via theclock line of the bus, to the slave IC, which receives both the clocksignal and digital data signals via the data line of the bus. Like inFIG. 2, the master IC and the slave IC are both powered by a supplyvoltage VDD, which may originate from a common power supply or fromdifferent power supplies.

The transmitting master IC and the receiving slave IC can be mounted onone printed circuit board or on different printed circuit boards. Thedifferent circuit boards can be in one and the same apparatus with acommon housing, or they can be in different apparatuses placed closetogether or any distance apart. In any case there will have to be a datacommunication link between the transmitter and the receiver. The datacommunication link can be a cable, a wireless link or any suitable linkover the actual distance. In FIG. 3 a frame 10 a, 10 b indicates thisfact. Part of the frame is shown in broken lines indicating that theintegrated circuits can be mounted on one or two circuit boards anydistance apart. Although not shown, the same applies to the systems inFIGS. 2 and 4 as well.

In FIG. 4 the transmitting master IC and the receiving slave IC bothreceive a “low swing” system clock signal SYSCLK, which is processedinternally in each of the integrated circuits. The processing mayinclude amplification and regeneration of a proper waveform for furtheruse in the respective integrated circuits. Regenerated internal clocksignals iclk1 and iclk2, respectively, are supplied to interfacecircuits in the respective integrated circuits. The interface circuitsare referred to as low swing clocked interfaces, LSCI. Data areexchanged between the master IC and the slave IC in one or bothdirections via a serial input/output (SIO) bus with n lines. Theprotocol used may support multi-slave architectures.

FIG. 5 shows the signal waveforms in the system in FIG. 4. The signalwaveforms are not necessarily drawn to the same amplitude scale. Thesystem clock signal SYSCLK is a “low swing” clock signal. Two clocksignals iclk1 and iclk2 regenerated from the external low swing SYSCLKcan be used to perform a data transfer protocol on a bi-directionalline(s) SIO. In the master IC the rising edge of the internal clockiclk1 is used to generate data, and in the slave IC the falling edge ofthe internal clock iclk2 is used to sample data. Such a protocol, wheredata is generated by the transmitter at one edge of iclk1 and is sampledby the receiver on the other clock edge of iclk2 is quite common. In theexample shown in FIG. 5 the system clock resembles a sine wave signaland can in fact be a sine wave signal. The system clock signal SYSCLKhas no steep edges and no abrupt changes between its high and low levelsand thus contains much less higher harmonics than a traditionally usedsquare wave signal. Also, the amplitude of the system clock signalSYSCLK is smaller than the amplitudes of the regenerated internal clocksignals iclk1 and iclk2.

Basically, iclk1 and iclk2 are independent. Different types of clockprocessing and/or different implementation technology of the twointegrated circuits may cause the regenerated internal clock signalsiclk1 and iclk2 may have a considerable phase difference, which is alsoreferred to as “skew”, which may have to be compensated for. If the skewis deterministic, it is possible to run the serial interface at the samespeed or frequency as the system clock. If the skew is unknown ordifficult to estimate, it is preferred to clock the data channel at aclock frequency lower than the system clock, preferably lower than halfthe frequency of the system clock.

Low swing clocked interfaces according to the invention allowsynchronization methods as used in asynchronous buses. Receiver samplingof data may be automatically synchronized. In principle, the receiverdoes not know when transmission is started, and the receiver samples theserial input/output (SIO) line, until the first transition signifying abit is recognized, whereafter the receiver samples the data stream withthe defined data rate frequency. When the maximum data rate is lowcompared to the system clock, it is possible to introduce amulti-sampling circuit, whereby each data bit is sampled several times,and an average is calculated between the sampling points to determinethe value of the data bit.

Although only serial data interfaces have been described, it will beclear that the invention can also be used in connection with paralleldata interfaces with corresponding advantages.

It is seen that the system interfaces in FIGS. 2 and 3 require fewer pinconnections on the integrated circuits relative to the prior art systemin FIG. 1. This is an advantage.

Clock lines like the ones shown can be a source of EMI, because thelines may act as antennas radiating electromagnetic signals at highfrequencies, in particular at higher harmonics of the clock frequency.“Low swing” signals in general, and “low swing” clock signals inparticular, have a reduced content of higher harmonics, whereby theproblem of EMI is correspondingly reduced.

Further, electromagnetic interference (EMI) is reduced drastically insystems comprising fewer “full swing” digital signals. An abrupt signaltransition from one level to another creates short and steep currentpulses not only on the signal lines but also on the power supply lines.Such current pulses have a significant high frequency content, which maycause disturbances, not only locally but the disturbances may spread viapower supply lines to other circuits, which may thereby become noiseinfected. Using “low swing” clock signals on the clock lines instead of“full swing” clock signals reduces this problem.

Also, since “low swing” signals have reduced amplitude relative totraditional “full swing” signals, they are less power consuming.

In commercial systems, low swing clocked interfaces (LSCI) are estimatedto be operable with clock frequencies in the range from 1 to 50 MHz withdata rates from 0.5 to 25 Mbit/s. Below this range asynchronous busesmay be preferred since an additional clock is saved.

In systems where simplicity is required, low swing clocked interfaces(LSCI) are well suited. Simplicity in design also means simplicity insystem verification, which in turn leads to shorter time to market.Also, simple systems are less liable to failure and less vulnerable thanmore complicated systems.

Low swing clocked interfaces have benefits for applications where lowpower dissipation and low costs are of importance. Typical anticipatedapplications include cellular and cordless systems, global positioningsystem (GPS) receivers, laptop computers, personal digital assistants(PDA), and Bluetooth transmitters and receivers.

1. A system comprising: a transmitter capable of transmitting digital data, an interface connected to the transmitter, the interface having at least one data line for receiving and transmitting the digital data from the transmitter, and a clock line for transmitting a clock signal, a clock circuit for supplying, to the clock line, the clock signal alternating between two signal levels at a predetermined frequency, the two signal levels effecting a low swing to mitigate the generation of electromagnetic interference EMI, thereby providing timing information, a receiver connected to the interface so as to receive, from the interface, the digital data transmitted on the data line, and so as to receive the clock signal on the clock line, characterized in that the receiver regenerates an internal clock signal derived from the received clock signal and the receiver uses the clock signal received from the clock line for deriving the timing information for processing the received digital data.
 2. A system according to claim 1, characterized in that the clock circuit for supplying the clock signal to the clock line is included in the transmitter.
 3. A system according to claim 2, characterized in that the receiver receives, as the only clock signal, the clock signal transmitted by the transmitter.
 4. A system according to claim 1, characterized in that the clock circuit for supplying the clock signal to the clock line is a clock signal generator external to the transmitter.
 5. A system according to claim 1, characterized in that the transmitter and the receiver both receive a power supply voltage (VDD) and the two signal levels of the clock signal have a voltage difference that is less than the VDD.
 6. A system according to claim 1, characterized in that the receiver is also capable of transmitting digital data, the data line is capable of receiving and transmitting the digital data from the receiver, and the transmitter is capable of receiving the digital data from the interface.
 7. A system according to claim 1, wherein the transmitter and the receiver both receive a power supply voltage (VDD) and the two signal levels of the clock signal have a voltage difference that is less than half of the VDD.
 8. A system according to claim 1, wherein the clock signal is a sine wave signal to mitigate the generation of EMI.
 9. A system according to claim 1, wherein the clock signal is a sine wave signal to mitigate the generation of EMI, the transmitter and the receiver both receive a power supply voltage (VDD), and the two signal levels of the clock signal have a voltage difference that is less than the VDD.
 10. A system according to claim 1, wherein the clock signal is a sine wave signal to mitigate the generation of EMI, the transmitter and the receiver both receive a power supply voltage (VDD), and the two signal levels of the clock signal have a voltage difference that is less than half of the VDD.
 11. A system according to claim 1, wherein the clock line does not transmit digital data.
 12. A system according to claim 1, wherein the internal clock signal is regenerated by reshaping the received clock signal from a sine wave signal into a square wave signal and by amplifying the received clock signal.
 13. A system comprising: a transmitter to transmit digital data; an interface connected to the transmitter, the interface having at least one data line for receiving and transmitting the digital data from the transmitter, and a clock line for transmitting a clock signal; a clock circuit to supply a low swing clock signal to the clock line thereby providing timing information, the low swing clock signal alternating between two signal levels at a predetermined frequency, the two signal levels having a voltage difference that is less than one half a power supply voltage (VDD); a receiver connected to the interface to receive the digital data transmitted on the data line and to receive the low swing clock signal on the clock line as the only clock signal for deriving the timing information for processing the received digital data, the receiver further receives the power supply voltage (VDD) and amplifies and reshapes the received low swing clock signal to thereby regenerate a usable internal clock signal.
 14. The system of claim 13, wherein the low swing clock signal mitigates generation of electromagnetic interference EMI. 